With many devices now using smaller and smaller die sizes, signal rise and fall times are getting much faster. This makes signal integrity analysis an important design consideration even for relatively low clock speeds.

We perform signal integrity simulation at Schematic and PCB level. This allows us to identify and eliminate crosstalk and signal reflections with suitable impedance matching and termination. FPGA signals can also be analysed to provide optimum performance.

Plot showing multiple termination options during development